In the IEEE JSSC paper reference (K. Lee, M. R. Miller and G. C. Temes, “An 8.1 mW, 82 dB Delta-Sigma ADC with 1.9 MHz BW and −98 dB THD,”, IEEE J. Solid State Circuits, vol. 44, no. 8, pp. 2202-2211, August 2009), a delta sigma analog-to-digital converter (ADC) with quantization noise coupling (QNC) is presented. The quantization noise coupling is a transposition on the analog domain of the truncation error feedback largely used in the digital domain. The idea is that the quantization noise error made by the quantizer of the ADC is memorized and fed back to the quantizer input so that this error is integrated in the next samples processing. FIG. 1 shows block diagrams of respective examples of how this can be done. For example, FIG. 1 shows that the difference between the analog sample and the actually converted digital sample is processed by subtracting the respective values and storing them for the next sample where this error is subtracted from the input value. This results in a transportation to the analog domain of the truncation error feedback used in digital filtering. Thus, the quantization error is stored in memory to not lose any information and to make sure that this information is properly integrated at the next sample. This furthermore implies a noise shaping of the quantization noise and therefore implies a better signal to quantization noise ratio (SNQR). This leads to a much better signal to quantization noise ratio because the error that is made by the quantizer is not lost at each sample, but is reintegrated to the signal to quantize at each sample. Table 1 shows the difference between a conventional sigma delta ADC and an improved sigma delta ADC using quantization noise coupling (QNC) depending on a selected oversampling rate (OSR).
TABLE 1OSR (oversampling rate)163264128256512SNQR59 dB74 dB89 dB102 dB112 dB128 dB(2nd ordersingle loopwith 5 levelDAC)SNQR64 dB81 dB96 dB112 dB126 dB140 dB(2nd ordersingle loopwith 5 levelDACwith QNC,same loopcoefficients)
The implementation of this quantization noise coupling is described in the aforementioned reference article and uses a feed forward summation amplifier (a feed forward summation amplifier is often used in delta-sigma ADC to provide low distortion transfer functions). By adding multiple capacitors in ping pong on the feedback of the amplifier and by adding phases to control these capacitors, the quantization error feedback is realized. This implementation needs additional capacitors and control phases and an additional digital-to-analog converter (DAC) with an additional delay for the signals at the input of this additional DAC (See Figure II of the reference article).
This implementation may be cumbersome and not adapted to a DAC implementation that requires two phases to process the DAC output (like the 5-level DAC described in commonly owned U.S. Pat. No. 7,102,558, which is hereby incorporated in its entirety by reference herein for all purposes). FIG. 8 shows a circuit diagram of the DAC related portion and integrator according to U.S. Pat. No. 7,102,558 which is capable of generating five different voltage levels. As shown in FIG. 8, depicted is a schematic circuit diagram of capacitor switching arrays and a differential amplifier for a five level feed-back digital-to-analog converter (DAC). The five-level feed-back DAC, generally represented by the numeral 100, comprises a switching sequence that generates five equally spaced charge quantities during two phases (precharge+transfer) of a differential charge transfer. Thus, the five equally distributed charge levels may be C*VREF, C*VREF/2, 0, −C*VREF/2 and −C*VREF. The reference voltage (VREF=VREFP−VREFM) charging circuit is generally represented by the numeral 102 and comprises transfer reference capacitors 132a and 132b, and switches 112, 114 and 116. The remainder of the specific exemplary embodiment comprises voltage input capacitors 130a and 130b, switches 104, 106, 108 and 110, and differential operational amplifier 150 having feed-back sampling capacitors 134a and 134b. Switches 108a and 108b may relate to common mode operation, and switch 108c may relate to differential signal operation.
VREFP and VREFM represent voltages at the differential reference input terminals. The reference voltage VREF=VREFP−VREFM. VINP and VINM represent voltages at the differential input signal terminals. The input signal voltage VIN=VINP−VINM. The transfer reference capacitors 132a and 132b may be equal to C/2. The input sampling capacitors 130a and 130b may be equal to A*C/2. The feed-back capacitors 134a and 134b may be equal to C. The input voltage is: VIN=VINP−VINM, and the output voltage is: VOUT=VOUTP−VOUTM. The gain of the circuit shown is A.
Switching sequences for these five levels are shown in FIGS. 9a-9e. The switching sequences of the switches 104-116 used to obtain the five equally distributed charge levels C*VREF, C*VREF/2, 0, −C*VREF/2 and −C*VREF of the specific exemplary circuit illustrated in FIG. 8. A “1” logic level depicts the respective switches in the closed position and a “0” logic level depicts the respective switches in the open position. FIGS. 9a-9e further illustrate the non-overlapping delays between the switches 104-116 in order to prevent a short between inputs and to ensure that the switches connected to the summing node always open first. The switches 104-116 are all open (off-logic 0) between time 202 and time 204. Time 202 signifies the end of the charging phase of the transfer reference capacitors 132a and 132b, and the sampled VIN charge on the input capacitors 130a and 130b. Time 204 signifies the beginning of the transfer phase of the charge on the transfer reference capacitors 132a and 132b. 
FIG. 2 shows a single ended implementation according to the above mentioned article for a better readability. However, the actual implementation would be fully differential. As can be seen, this implementation needs an additional digital-to-analog converter (DAC), additional delayed signals for the DAC input and a complex ping-pong feedback capacitor network in the summing amplifier which as mentioned is cumbersome to implement as it needs additional phases as well as many additional switches in the feedback of the operational amplifier. FIG. 2 shows that the phases are split between odd and even phases.
In this conventional embodiment as shown in the circuit diagram and associated table in FIG. 2, the quantization happens at the end of phase P1, the quantization feedback DAC samples in the next phase P1 and transfers in the next phase P2, with one sample delay, whereas the main DAC samples in phase P2 of the same sample and transfers in phase P1 of the next one, with no delay. Hence, this conventional concept requires a complex implementation which is undesirable.